1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a method and apparatus for driving the data in an LCD panel.
2. Description of the Related Art
A typical LCD device displays an image on an image display unit via liquid crystal cells arranged in a matrix format by controlling light transmittance in response to a video signal. An active-matrix LCD device, in particular, uses a thin film transistor (TFT), which is a well-known switching element, to drive the pixels. The TFT utilizes an amorphous silicon (a-Si) thin film or a low temperature polycrystalline silicon (LTPS) thin film. The LTPS thin film, which is formed by crystallizing the a-Si thin film by a laser annealing method, allows a driving circuit of the image display unit to be mounted on a substrate because the LTPS thin film shows high electron mobility and can achieve a highly integrated circuit.
The LCD device where the LTPS thin film is used and the driving circuit is mounted on the substrate supplies data to the image display unit by a block sequential driving method. When using the block sequential driving method, the LCD device using the LTPS thin film splits data lines into a plurality of blocks and drives the data lines sequentially, block-by-block, during one horizontal period. However, in the block-based sequential driving method, a data voltage charged to a pixel electrode connected to the last data line of each block varies by the interference of a data signal supplied to the first data line of the next block during a data charge of the next block and therefore picture quality degradation occurs from a block boundary.
Hereinafter, description of how the block boundary is generated in a conventional block sequential driving method will be provided with reference to FIG. 1.
FIG. 1 is a circuit diagram illustrating a part of a TFT substrate of a conventional LCD panel using an LTPS thin film, focusing on a data driver. The LCD panel includes a data driver 10 mounted therein with shift registers SRm and SRm+1 and sampling blocks SBm and SBm+1 for sequentially driving blocks of data lines DLm1 . . . DLmn and DL(m+1)1 . . . DL(m+1)n of an image display unit 20.
The image display unit 20 includes pixel electrodes 12 formed at subpixel regions defined by the intersections of gate lines GLi and GLi+1 and the data lines DLm1 to DL(m+1)n, and TFTs for independently driving the pixel electrodes 12. The gate lines GLi and GLi+1 are sequentially driven by a gate driver (not shown) mounted on the LCD panel. The data lines DLm1 . . . DLmn and DL (m+1)1 . . . DL(m+1)n are sequentially driven block-by-block every horizontal period during which the gate lines GLi and GLi+1 are driven and charge data signals supplied through the data driver 10. The TFTs maintain the data signals of the data lines DLm1 . . . DLmn and DL(m+1)1 . . . DL(m+1)n by charging them to the voltage of the pixel electrodes 12 in response to scan signals of the gate lines GLi and GLi+1.
The data driver 10 sequentially drives the data lines DLm1 . . . DLmn and DL(m+1)1 . . . DL(m+1)n of the image display unit 20 in blocks PBm, PBm+1 and supplies data signals D1 to Dn transmitted through data buses B1 to Bn to the pixel blocks PBm and PBm+1. The m-th and (m+1)-th shift registers SRm and SRm+1 of the data driver 10 sequentially provide sampling control signals. S ampling switches SW1, SW2, . . . SWn of the m-th sampling block SBm perform sampling of the n data signals D1, D2, . . . Dn supplied through the n data buses B1, B2, . . . Bn in response to the sampling control signals of the m-th shift register SRm, and charge the sampled signals to the n data lines DLm1 to DLmn of the m-th pixel block PBm. Th en the TFTs of the m-th pixel block PBm that are tumed on by the driving of the gate lines GLi and GLi+1 charge the data lines DLm1 to DLmn to the pixel electrodes 12. The (m+1)-th shift register and sampling block SRm+1 and SBm+1 are identically driven to perform sampling of the n data signals D1 to Dn supplied through the data buses B1 to Bn and charge the sampled signals to the data lines DL(m+1)1 to DL(m+1)n of the (m+1)-th pixel block PBm+1. Then the TFTs of the (m+1)-th pixel block PBm+1 that are turned on by the driving of the gate lines GLi and GLi+1 charge the data lines DL(m+1)1 to DL(m+1)n to the pixel electrodes 12.
When the data signals are charged to the data line DL(m+1)1 to DL(m+1)n of the (m+1)-th pixel block PBm+1, the data signal to the pixel electrode 12 that is connected to the last data line DLmn of the m-th pixel block PBm varies by the interference of the data signal charged to the first data line DL(m+1)1 of the (m+1)-th pixel block PBm+1. This is caused by a coupling of a parasitic capacitance Cp formed between the pixel electrode 12 connected to the last data line DLmn of the m-th pixel block PBm and the first data line DL(m+1)1 of the (m+1)-th pixel block PBm+1. Therefore, a defect is generated at a boundary between the m-th pixel block PBm and the (m+1)-th pixel block PBm+1.